M50734SP Architecture

The M50734SP is a member of Mitsubishi's 740 Series (also written "M740") family of CMOS 8-bit single-chip microcomputers. The 740 Series is broadly 6502-compatible but with a significantly extended instruction set, additional addressing modes, on-chip peripherals, and built-in bit-manipulation instructions that make it highly suited to embedded control applications.

The "SP" suffix denotes the extended variant without on-chip program ROM — program memory is supplied externally, making it ideal for development. Production variants of the 740 family include on-chip ROM.

Registers

Register Width Name Description
A8-bitAccumulatorPrimary arithmetic and logic register. Many instructions implicitly use A.
X8-bitIndex Register XIndexing, loop counting, offset addressing.
Y8-bitIndex Register YIndexing, loop counting, offset addressing.
SP8-bitStack PointerPoints to the top of the stack (page 1: $0100–$01FF). Decrements on push.
PC16-bitProgram CounterPoints to the next instruction byte to be fetched.
P8-bitProcessor StatusCondition flags — see below.

Processor Status Register (P)

Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
N V T B D I Z C
Negative Overflow T-flag
(740 unique)
Break Decimal IRQ Disable Zero Carry

T flag (Bit 5) is unique to the 740 Series. When set, certain instructions operate in a special transfer mode, allowing memory-to-memory operations without disturbing the accumulator. Instructions that use the T flag are marked [T] in the instruction reference.

Addressing Modes

The M50734SP supports the following addressing modes:

ModeSyntaxDescription
ImpliedINXOperand is implied by the instruction.
AccumulatorASL AOperates on the accumulator.
ImmediateLDA #$42Operand is the next byte in the instruction stream.
Zero PageLDA $10Single-byte address within page 0 ($0000–$00FF).
Zero Page, XLDA $10,XZero page address plus X register.
Zero Page, YLDX $10,YZero page address plus Y register.
AbsoluteLDA $1234Full 16-bit address.
Absolute, XLDA $1234,X16-bit address plus X register.
Absolute, YLDA $1234,Y16-bit address plus Y register.
(Indirect, X)LDA ($10,X)Pre-indexed indirect: zero page address + X gives pointer.
(Indirect), YLDA ($10),YPost-indexed indirect: zero page pointer then add Y.
IndirectJMP ($1234)JMP only: 16-bit indirect pointer.
RelativeBEQ labelSigned 8-bit offset from next instruction (branch instructions).
Bit, Zero PageSEB 3,$10740-specific: bit number (0–7) and zero page address.
Bit, Zero Page, RelativeBBC 3,$10,label740-specific: bit test and branch.
Special PageJAL $F300740-specific: special-page direct jump to $FFxx.

On-Chip Peripheral Summary

PeripheralBase AddressNotes
I/O Port 0$F3–$F78-bit bidirectional port; P0-6 shared with UART TxD
I/O Port 1$F3–$F48-bit bidirectional port
I/O Port 2$F1–$F28-bit bidirectional port
I/O Port 3$DA–$DC8-bit bidirectional port
UART$E4–$E7Async serial; 9600 baud @ 7.3728 MHz on the board
Timer A / B$F8–$FCMulti-function 8-bit timers; UART baud rate generator
Timer 1/2/3$E0–$E316-bit interval timers
PWM$DD–$DFPulse-width modulation output
A/D Converter$E9–$EB4-channel 8-bit ADC; channels AN0–AN3
Watchdog$FEReset circuit; must be serviced periodically
Interrupt controllerVectors at $FFF4–$FFFFMultiple vectored interrupts

Detailed Peripheral Documentation →