M50734SP Architecture
The M50734SP is a member of Mitsubishi's 740 Series (also written "M740") family of CMOS 8-bit single-chip microcomputers. The 740 Series is broadly 6502-compatible but with a significantly extended instruction set, additional addressing modes, on-chip peripherals, and built-in bit-manipulation instructions that make it highly suited to embedded control applications.
The "SP" suffix denotes the extended variant without on-chip program ROM — program memory is supplied externally, making it ideal for development. Production variants of the 740 family include on-chip ROM.
Registers
| Register | Width | Name | Description |
|---|---|---|---|
A | 8-bit | Accumulator | Primary arithmetic and logic register. Many instructions implicitly use A. |
X | 8-bit | Index Register X | Indexing, loop counting, offset addressing. |
Y | 8-bit | Index Register Y | Indexing, loop counting, offset addressing. |
SP | 8-bit | Stack Pointer | Points to the top of the stack (page 1: $0100–$01FF). Decrements on push. |
PC | 16-bit | Program Counter | Points to the next instruction byte to be fetched. |
P | 8-bit | Processor Status | Condition flags — see below. |
Processor Status Register (P)
| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 |
|---|---|---|---|---|---|---|---|
| N | V | T | B | D | I | Z | C |
| Negative | Overflow | T-flag (740 unique) |
Break | Decimal | IRQ Disable | Zero | Carry |
T flag (Bit 5) is unique to the 740 Series. When set, certain instructions operate in a special transfer mode, allowing memory-to-memory operations without disturbing the accumulator. Instructions that use the T flag are marked [T] in the instruction reference.
Addressing Modes
The M50734SP supports the following addressing modes:
| Mode | Syntax | Description |
|---|---|---|
| Implied | INX | Operand is implied by the instruction. |
| Accumulator | ASL A | Operates on the accumulator. |
| Immediate | LDA #$42 | Operand is the next byte in the instruction stream. |
| Zero Page | LDA $10 | Single-byte address within page 0 ($0000–$00FF). |
| Zero Page, X | LDA $10,X | Zero page address plus X register. |
| Zero Page, Y | LDX $10,Y | Zero page address plus Y register. |
| Absolute | LDA $1234 | Full 16-bit address. |
| Absolute, X | LDA $1234,X | 16-bit address plus X register. |
| Absolute, Y | LDA $1234,Y | 16-bit address plus Y register. |
| (Indirect, X) | LDA ($10,X) | Pre-indexed indirect: zero page address + X gives pointer. |
| (Indirect), Y | LDA ($10),Y | Post-indexed indirect: zero page pointer then add Y. |
| Indirect | JMP ($1234) | JMP only: 16-bit indirect pointer. |
| Relative | BEQ label | Signed 8-bit offset from next instruction (branch instructions). |
| Bit, Zero Page | SEB 3,$10 | 740-specific: bit number (0–7) and zero page address. |
| Bit, Zero Page, Relative | BBC 3,$10,label | 740-specific: bit test and branch. |
| Special Page | JAL $F300 | 740-specific: special-page direct jump to $FFxx. |
On-Chip Peripheral Summary
| Peripheral | Base Address | Notes |
|---|---|---|
| I/O Port 0 | $F3–$F7 | 8-bit bidirectional port; P0-6 shared with UART TxD |
| I/O Port 1 | $F3–$F4 | 8-bit bidirectional port |
| I/O Port 2 | $F1–$F2 | 8-bit bidirectional port |
| I/O Port 3 | $DA–$DC | 8-bit bidirectional port |
| UART | $E4–$E7 | Async serial; 9600 baud @ 7.3728 MHz on the board |
| Timer A / B | $F8–$FC | Multi-function 8-bit timers; UART baud rate generator |
| Timer 1/2/3 | $E0–$E3 | 16-bit interval timers |
| PWM | $DD–$DF | Pulse-width modulation output |
| A/D Converter | $E9–$EB | 4-channel 8-bit ADC; channels AN0–AN3 |
| Watchdog | $FE | Reset circuit; must be serviced periodically |
| Interrupt controller | Vectors at $FFF4–$FFFF | Multiple vectored interrupts |